Freescale Semiconductor /MKW21Z4 /XCVR_PHY_REGS /CFG1

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Interpret as CFG1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AA_PLAYBACK)AA_PLAYBACK 0 (0)AA_OUTPUT_SEL 0 (FSK_BIT_INVERT)FSK_BIT_INVERT 0 (RFU00)RFU00 0 (0)BSM_EN_BLE 0 (0)DEMOD_CLK_MODE 0CTS_THRESH0 (0)FSK_FTS_TIMEOUT 0 (RFU01)RFU01 0 (RFU02)RFU02 0BLE_NTW_ADR_THR

BSM_EN_BLE=0, AA_OUTPUT_SEL=0, DEMOD_CLK_MODE=0, FSK_FTS_TIMEOUT=0

Description

PHY CONFIGURATION REGISTER 1

Fields

AA_PLAYBACK

Access Address Playback

AA_OUTPUT_SEL

Access Address Output Select

0 (0): demodulated

1 (1): matched

FSK_BIT_INVERT

FSK Bit Invert

RFU00

Reserved for future use.

BSM_EN_BLE

BLE Bit Streaming Mode Enable bit

0 (0): BSM for BLE disabled

1 (1): BSM for BLE enabled

DEMOD_CLK_MODE

Demodulator Clock Mode

0 (0): Normal

1 (1): Demodulate all samples

CTS_THRESH

CTS (Coarse Timing Search) Correlation Threshold

FSK_FTS_TIMEOUT

FSK FTS Timeout

0 (0): 4 symbols

1 (1): 5 symbols

2 (2): 6 symbols

3 (3): 7 symbols

4 (4): 8 symbols

5 (5): 9 symbols

6 (6): 10 symbols

7 (7): 11 symbols

RFU01

Reserved for future use.

RFU02

Reserved for future use.

BLE_NTW_ADR_THR

BLE Network Address Match Bit Error Threshold

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